FWRISC
3 parts, in reading order.
FWRISC: Designing an FPGA-friendly Core in 30 Days
[](/legacy-img/fwriscintrosplash2.png) Designing a processor is often considered to be a large and complex undertaking, so how did I decide to design and implement in a month? For a few reasons, really. For one, my background is in hardware design, despit…
FWRISC: Sizing up the RISC-V Architecture
[](/legacy-img/post2intro.png) After deciding on October 22nd to create a RISC-V implementation to enter in the [2018 RISC-V soft-core contest](https://riscv.org/2018contest/) (with entries due November 26th), I needed to gather more information of th…
FWRISC: Creating a Unit-test Safety Net
[](/legacy-img/unittestsplash.png) When developing software, I've become very comfortable with test-driven development -- a methodology that calls for tests to be developed along with, or even before, functionality. It's quite common for me to develop a …