RISC-V
9 posts
SoC Integration Testing: Hw/Sw Test Coordination (Part 1)
[](/legacy-img/splash-9.png) IP- and subsystem-level testbenches are quite monolithic. There is a single entity (the testbench) that applies stimulus to the design, collects metrics, and checks results. In contrast, an SoC-level testbench is compose…
SoC Integration Testing: IP-Integrated Debug and Analysis
[](/legacy-img/splash-8.png) One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I st…
SoC Integration Testing: Higher-Level Software Debug Visibility
[](/legacy-img/splash-14.png) Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping…
SoC Integration Testing: Intro and Challenges
[](/legacy-img/splash.png) As I mentioned in my [end-of-year post](/blog/2020-nights-and-weekends-projects-in-review/), one of my 2020 projects was to develop a design for the [Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run](https://efable…
2020: Nights and Weekends Projects in Review
[](/legacy-img/splash-2.png) 2020 in Review Last year was my first year-end blog post looking back at the prior year's projects, and I thought I'd continue the (now) tradition this year. 2020 has definitely been a different year for me, and not just bec…
FWRISC: Creating a Unit-test Safety Net
[](/legacy-img/unittestsplash.png) When developing software, I've become very comfortable with test-driven development -- a methodology that calls for tests to be developed along with, or even before, functionality. It's quite common for me to develop a …
FWRISC: Sizing up the RISC-V Architecture
[](/legacy-img/post2intro.png) After deciding on October 22nd to create a RISC-V implementation to enter in the [2018 RISC-V soft-core contest](https://riscv.org/2018contest/) (with entries due November 26th), I needed to gather more information of th…
FWRISC: Designing an FPGA-friendly Core in 30 Days
[](/legacy-img/fwriscintrosplash2.png) Designing a processor is often considered to be a large and complex undertaking, so how did I decide to design and implement in a month? For a few reasons, really. For one, my background is in hardware design, despit…
Chisel Sharpening: Initial impressions
Recently, RiscV () has been all the rage. The free (as in speech and beer) instruction-set architecture has experienced an explosion of interest in the last couple of years, after being more-or-less an academic curiosity since 2010 or so. This post isn't …