FWRISC
6 posts
Selectively Muting your BFMs to Speed up Simulation
[](/legacy-img/splash-7.png) Have you ever had the misfortune to be on the CC list for a "lively" email discussion where you're a stakeholder but only case about the conclusion? You can't simply ignore the traffic, because you do care about the conclusio…
2019 - The "Nights and Weekends Projects" Year in Review
[](/legacy-img/splash-16.png) It's almost the end of 2019, and I've been thinking back over the year as well as thinking ahead to 2020. In past years, I've often evaluated my "nights and weekends" projects using the same metrics I'm evaluated on at work:…
Py-HPI: Applying Python for Verification
[](/legacy-img/splash-5.png) Intro In my [last post](/blog/py-hpi-a-procedural-hdl-python-integration/), I talked about a prototype procedural interface between Python and HDL that enables cross-calling between Python and SystemVerilog. My primar…
FWRISC: Creating a Unit-test Safety Net
[](/legacy-img/unittestsplash.png) When developing software, I've become very comfortable with test-driven development -- a methodology that calls for tests to be developed along with, or even before, functionality. It's quite common for me to develop a …
FWRISC: Sizing up the RISC-V Architecture
[](/legacy-img/post2intro.png) After deciding on October 22nd to create a RISC-V implementation to enter in the [2018 RISC-V soft-core contest](https://riscv.org/2018contest/) (with entries due November 26th), I needed to gather more information of th…
FWRISC: Designing an FPGA-friendly Core in 30 Days
[](/legacy-img/fwriscintrosplash2.png) Designing a processor is often considered to be a large and complex undertaking, so how did I decide to design and implement in a month? For a few reasons, really. For one, my background is in hardware design, despit…