FPGA
4 posts
FWRISC: Sizing up the RISC-V Architecture
[](/legacy-img/post2intro.png) After deciding on October 22nd to create a RISC-V implementation to enter in the [2018 RISC-V soft-core contest](https://riscv.org/2018contest/) (with entries due November 26th), I needed to gather more information of th…
FWRISC: Designing an FPGA-friendly Core in 30 Days
[](/legacy-img/fwriscintrosplash2.png) Designing a processor is often considered to be a large and complex undertaking, so how did I decide to design and implement in a month? For a few reasons, really. For one, my background is in hardware design, despit…
Make Your Prototype Board Cloud-Accessible
[](/legacy-img/IntroPicture.png) FPGA prototype boards are an important component of the hardware development process, and the progress of synthesizing a design, uploading it to the prototype, and validating its behavior has definitely become easier …
Chisel Sharpening: In the end, it's all about results
At the end of the day, it's all about results, of course. A productivity improvement is great, as long as the implementation results at least stay constant. Any decrease in implementation results definitely detract from any productivity improvements. So, …