Zuspec
11 posts
Getting Started with Executable Specs
Hardware engineers spend their lives working with specifications, both natual language ("paper") and executable. We've been looking at characterizing the interfaces and internal implementation of executable specifications -- models. But, enough theory. Let's …
Relating Hardware Model Abstractions
The most difficult transition in hardware modeling is the transition from natural-language to executable specification. It is during this transition that the ambiguities inherent in natural-language descriptions are resolved. Maximizing value from a multi-abst…
Shifting Left with Hardware Model Abstractions
"Shift-Left" is a strategy to reorganize processes to enable more parallelism by adjusting dependencies. Hardware model abstractions provide a key tool to shifting tasks left in the silicon design process.
The Best of a Language and a Class Library
In hardware design and verification, we're used to working with domain-specific languages (DSLs), such as SystemVerilog, VHDL, and PSS, as well as class libraries, such as UVM, SystemC, and CHISEL. We use these DSLs and class libraries to capture key semantic…
Zuspec: Pythonic Model-Driven Hardware Development
Designing and implementing hardware is challenging, and is getting more difficult each year as systems become more complex. Design and verification teams are looking to boost productivity as a way to keep pace, while also looking for ways to provide models …
AI: Instigating a Developer Docs Renaissance?
There's been lots of discussion about the future of writing in the AI age. LLMs have shown their potential as a tool by helping authors of many genres brainstorm ideas, rough out content, and more. But, this automation comes with questions attached. If writin…
Re-Evaluating EDA DSLs: Becoming the Compiler
A key benefit of full languages is having full control over processing the language: being the compiler. Having full control over language processing is exactly what enables us target simulation and FPGA bitstream with the same SystemVerilog source simply by …
Re-Evaluating EDA DSLs in the AI Era
I've been looking for a new hardware-centric design language for the last couple of years. Or, more precisely, I've been looking for a hardware-centric design language that would allow me to realize my ideal silicon design flow. - Must support using the same…
PSS: Getting Outside the Box
In the [last post](https://bitsbytesgates.com/pss/2025/02/04/TranspilationandPSS.html), we showed a SystemVerilog implementation of a PSS model that printed "Hello World!". Interesting, perhaps, but quite a ways from being useful. In order to be useful, our …
Transpilation and PSS
You're probably familiar with compilers. They take a high-level input description -- typically a programming language -- and distill it down to an efficient low-level implementation. Typically the implementation is machine code or bytecode. In other words, …
What's Next for PSS?
As the year winds down, it's a good time to think about the coming year and the areas where I'd like to have an impact. One area of particular interest this year is the Portable Test and Stimulus (PSS) standard. The Accellera PSS working group released the 3.…