SystemVerilog
21 posts
Embracing UVM for FOSSi Design Verification
Open source communities emphasize reuse and collaboration centered around open and standard data formats. While open source communities do exist in cases where closed-source tools provide the sole implementation of a standard, these communities have significa…
Introducing SV/UVM to Python Development Tools
Over the past few posts, we've examined the details of dynamically interacting with a SystemVerilog/UVM environment from Python. We can access the component hierarchy of a UVM testbench, read and write the value of sequence-item fields, and run sequences from…
Working with Analysis Ports
For the most part, UVM and SystemVerilog make interactions with a dynamically-typed language surprisingly easy. There are a few exceptions where the developer of the SystemVerilog UVM code must step in to enable access to certain testbench elements. Analysis …
Accessing User-Defined SV Data from Python
We've seen how the [PyHDL-IF](http://github.com/fvutils/pyhdl-if) library makes it simple to implement UVM sequences and components in Python, and how Python can call back into SystemVerilog. But, a significant part of a testbench deals with user-defined data…
The Mechanics of UVM/Python Cross-Calling
It's not necessary to understand very much about how PyHDL-IF implements the bridge between Python and UVM, but useful to understand a bit. Doing so helps to understand what this library is and is not intended to do, and how you can best use it in your verifi…
PSS: Getting Outside the Box
In the [last post](https://bitsbytesgates.com/pss/2025/02/04/TranspilationandPSS.html), we showed a SystemVerilog implementation of a PSS model that printed "Hello World!". Interesting, perhaps, but quite a ways from being useful. In order to be useful, our …
Transpilation and PSS
You're probably familiar with compilers. They take a high-level input description -- typically a programming language -- and distill it down to an efficient low-level implementation. Typically the implementation is machine code or bytecode. In other words, …
Easy Access to Python Libraries with a SystemVerilog Convenience API
In the last post ([DPI Isn't Enough: Making Python Part of Your SV Testbench](https://bitsbytesgates.com/python/2024/11/04/DPIIsntEnoughMakingPythonPartOfYourSVTB.html)), we looked at how to use the [PyHDL-IF](https://fvutils.github.io/pyhdl-if) library to …
DPI Isn't Enough: Making Python Part of Your SV Testbench
I've been using Python for verification since early 2019 for personal projects, and have found both the language and the rich ecosystem of general and special-purpose libraries to be incredibly helpful in quickly and efficiently bringing up a testbench enviro…
Relating Actions with Dataflow
Modularity and reuse are key concerns when it comes to programming languages. While languages without many modularity and reuse features may be quick and easy to write -- think shell scripts -- they ultimately fail to scale. PSS provides a wealth of mechanism…
TbLink-RPC: Simplifying the Multi-Language Testbench
[](/legacy-img/MultiLanguageTestbenchsplash.png) SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s oft…
Documenting SystemVerilog with Sphinx
[](/legacy-img/documenting-systemverilog-with-sphinx-3.png) I've been digging into a project over the last few months whose value proposition is to simplify the process of connecting simulation-like environments and things like reference models, testbenc…
Arrays, Dynamic Arrays, Queues: One List to Rule them All
[](/legacy-img/splash-13.png) Randomizable lists are, of course, very important in modeling more-complex stimulus, and I've been working to support these within PyVSC recently. Thus far, PyVSC has attempted to stay as close as possible to both the feature…
Py-HPI: A Procedural HDL/Python Integration
[](/legacy-img/splash-15.png) As I mentioned in my [last post](/blog/functional-verification-and-the-ecosystem-argument/), I've been looking at using Python for more tasks, including functional verification. My go-to languages for functional verifi…
Why Not an IDE?
As anyone (technical) who knows me can attest, I'm a big fan of Integrated Development Environments (IDEs). I've personally focused particularly on the [Eclipse](http://eclipse.org/) IDE, but I'm more generally a fan of the concept -- the notion that the task …
DVKit: Setting up SystemVerilog Development
[](/legacy-img/Headlinefull-2.png) In my [last post](/blog/dvkit-workspaces-projects-and-legacy-code/) on DVKit, I described how Eclipse uses projects to group source files, and uses workspaces to organize the projects and settings for a given developmen…
DVKit: Workspaces, Projects, and Legacy Code
In [Part 1](/blog/dvkit-more-productive-code-development-for-dv-engineers/) of this series, I introduced DVKit, an Eclipse-based IDE for files types used by DV engineers. If you're used to editing your source files with a single-file editor like Vi/Vim or Emac…
DVKit: More-productive Code Development for DV Engineers
[](/legacy-img/BlogHeadline.png) If you're a design verification (DV) engineer, how many different languages do you code in every day? If you're like me, the number is significant. On any given day, I might find myself working on SystemVerilog, PERL, …
Designing Standard-protocol Interfaces with Chisel Bundles
[](/legacy-img/plugboard2.jpg) Standard interfaces are all around us, and enhance interoperability between devices created by different organizations. While some standard interfaces are quite niche in nature, others, like the unbiquitous phono jack, have …
Chisel Sharpening: Initial impressions
Recently, RiscV () has been all the rage. The free (as in speech and beer) instruction-set architecture has experienced an explosion of interest in the last couple of years, after being more-or-less an academic curiosity since 2010 or so. This post isn't …
SVEditor: What's that reference? (Part 1)
One key feature of integrated development environments -- especially those for object oriented languages -- is the ability to find the references to a data type, a method, or a data field. A few months back, I implemented initial reference-finding functionalit…