Python
43 posts
The Right Skills for the Job: Project-Scoped Agent Skills
Agentic AI has quickly become a dominant workflow. Give an LLM access to the filesystem and shell, provide it good instructions, and watch it work! It's that second part that is critical to making the process scalable. LLMs are quite happy to fill in the gaps…
What's My Env Again?
Almost any non-trivial project will require some amount of environment configuration. Perhaps the project uses a local Python virtual environment that must be used for running tests. Perhaps it's a hardware-design project that needs to configure the environmen…
Simplifying Access to Open-Source EDA Software
Free and Open-Source Silicon (FOSSi) hardware designs face an interesting challenge. There's a sizable and growing set of open source tools. But, obtaining the software in pre-built form -- especially the latest versions -- can be a challenge due to the numbe…
Managing DV Project Dependencies - Now with FuseSoc
I had the pleasure of attending [LatchUp](https://fossi-foundation.org/latch-up/2026) this past weekend. Conferences invariably spark new ideas and new perspectives, and this past weekend was no different. Specifically, I found a new perspective on interope…
Getting Started with Executable Specs
Hardware engineers spend their lives working with specifications, both natual language ("paper") and executable. We've been looking at characterizing the interfaces and internal implementation of executable specifications -- models. But, enough theory. Let's …
The Best of a Language and a Class Library
In hardware design and verification, we're used to working with domain-specific languages (DSLs), such as SystemVerilog, VHDL, and PSS, as well as class libraries, such as UVM, SystemC, and CHISEL. We use these DSLs and class libraries to capture key semantic…
Introducing SV/UVM to Python Development Tools
Over the past few posts, we've examined the details of dynamically interacting with a SystemVerilog/UVM environment from Python. We can access the component hierarchy of a UVM testbench, read and write the value of sequence-item fields, and run sequences from…
Working with Analysis Ports
For the most part, UVM and SystemVerilog make interactions with a dynamically-typed language surprisingly easy. There are a few exceptions where the developer of the SystemVerilog UVM code must step in to enable access to certain testbench elements. Analysis …
Accessing User-Defined SV Data from Python
We've seen how the [PyHDL-IF](http://github.com/fvutils/pyhdl-if) library makes it simple to implement UVM sequences and components in Python, and how Python can call back into SystemVerilog. But, a significant part of a testbench deals with user-defined data…
The Mechanics of UVM/Python Cross-Calling
It's not necessary to understand very much about how PyHDL-IF implements the bridge between Python and UVM, but useful to understand a bit. Doing so helps to understand what this library is and is not intended to do, and how you can best use it in your verifi…
Unlocking the Combined Strength of UVM and Python
UVM and Python are often positioned as rivals when it comes to their role in functional verification, with teams picking one or the other as the basis for a verification environments. Each have strengths, though, and using them together produces much strong…
Zuspec: Pythonic Model-Driven Hardware Development
Designing and implementing hardware is challenging, and is getting more difficult each year as systems become more complex. Design and verification teams are looking to boost productivity as a way to keep pace, while also looking for ways to provide models …
Re-Evaluating EDA DSLs: Becoming the Compiler
A key benefit of full languages is having full control over processing the language: being the compiler. Having full control over language processing is exactly what enables us target simulation and FPGA bitstream with the same SystemVerilog source simply by …
Re-Evaluating EDA DSLs in the AI Era
I've been looking for a new hardware-centric design language for the last couple of years. Or, more precisely, I've been looking for a hardware-centric design language that would allow me to realize my ideal silicon design flow. - Must support using the same…
Easy Access to Python Libraries with a SystemVerilog Convenience API
In the last post ([DPI Isn't Enough: Making Python Part of Your SV Testbench](https://bitsbytesgates.com/python/2024/11/04/DPIIsntEnoughMakingPythonPartOfYourSVTB.html)), we looked at how to use the [PyHDL-IF](https://fvutils.github.io/pyhdl-if) library to …
DPI Isn't Enough: Making Python Part of Your SV Testbench
I've been using Python for verification since early 2019 for personal projects, and have found both the language and the rich ecosystem of general and special-purpose libraries to be incredibly helpful in quickly and efficiently bringing up a testbench enviro…
New Year, New Space
We've more than gotten started on the new year. In fact, DVCon -- reliably and predictably held during the last few days of February and initial few of March is right around the corner. And, here I am just getting the first post of the year out. Getting a la…
Simplifying Custom Template-Generated Content
[](/legacy-img/splash-18.png) As a verification engineer, it's quite common to work with data and code that follow a regular pattern. Having an efficient way to create this repetitive code is a significant productivity boost. While there certainly are p…
PyUCIS: Manipulating Coverage Data
[](/legacy-img/splash-17.png) In a prior post, we looked at how to inspect coverage as a text report and export coverage data using the PyVSC API, and view coverage graphically using the PyUCIS-Viewer. Recent enhancements have enabled the PyUCIS library …
Tools and Techniques to Improve YAML-File Usability
[](/legacy-img/splash-19.png) This blog post is a bit of a departure from many that I’ve created for this blog. Most of my blog posts are about things I’ve created. This post is about a collection of tools that I use in developing the things I create. …
PyVSC: Working with Coverage Data
[](/legacy-img/pyvsccoverage-2.png) I’ve been investing some time in documentation updates this weekend, after a couple of [PyVSC](https://github.com/fvutils/pyvsc) users pointed out some under-described aspects of the PyVSC coverage flow. Given that th…
TbLink-RPC: Simplifying the Multi-Language Testbench
[](/legacy-img/MultiLanguageTestbenchsplash.png) SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s oft…
Documenting SystemVerilog with Sphinx
[](/legacy-img/documenting-systemverilog-with-sphinx-3.png) I've been digging into a project over the last few months whose value proposition is to simplify the process of connecting simulation-like environments and things like reference models, testbenc…
SoC Integration Testing: Hw/Sw Coordination (Part 2)
[](/legacy-img/splash-10.png) Controlling the outside world -- specifically interface BFMs -- from embedded software is critical to SoC integration tests that exercise interface IP. [In the last post](/blog/so-c-integration-testing-hw-sw-test-coordina…
SoC Integration Testing: IP-Integrated Debug and Analysis
[](/legacy-img/splash-8.png) One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I st…
SoC Integration Testing: Higher-Level Software Debug Visibility
[](/legacy-img/splash-14.png) Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping…
SoC Integration Testing: Intro and Challenges
[](/legacy-img/splash.png) As I mentioned in my [end-of-year post](/blog/2020-nights-and-weekends-projects-in-review/), one of my 2020 projects was to develop a design for the [Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run](https://efable…
2020: Nights and Weekends Projects in Review
[](/legacy-img/splash-2.png) 2020 in Review Last year was my first year-end blog post looking back at the prior year's projects, and I thought I'd continue the (now) tradition this year. 2020 has definitely been a different year for me, and not just bec…
Arrays, Dynamic Arrays, Queues: One List to Rule them All
[](/legacy-img/splash-13.png) Randomizable lists are, of course, very important in modeling more-complex stimulus, and I've been working to support these within PyVSC recently. Thus far, PyVSC has attempted to stay as close as possible to both the feature…
Python Verification Stimulus and Coverage: Constraints
[](/legacy-img/splashconstraints.png) Over the past few blog posts, we've looked at: - [The fundamentals of modeling stimulus and functional coverage in Python](/blog/modeling-random-stimulus-and-functional-coverage-in-python/) - [Modeling verificati…
Python Verification: Working with Coverage Data
[](/legacy-img/splash-4.png) Before jumping into this week's post, I wanted to offer a bit of an apology to my readers. I recently realized that, despite being a Google property, Blogger only notifies authors of comments for moderation if the author h…
Python Verification Stimulus and Coverage: Functional Coverage
[](/legacy-img/pyvsccoverage.png) In my last two posts ([here](/blog/modeling-random-stimulus-and-functional-coverage-in-python/) and [here](/blog/python-verification-stimulus-and-coverage-data-types/)), I've been talking about modeling random stimulus, …
Python Verification Stimulus and Coverage: Data Types
[](/legacy-img/ModelingRandomStimulusSplash-2.png) In my last post, [Modeling Random Stimulus and Functional Coverage in Python](/blog/modeling-random-stimulus-and-functional-coverage-in-python/), I introduced a Python library for modeling random vari…
Modeling Random Stimulus and Functional Coverage in Python
[](/legacy-img/ModelingRandomStimulusSplash.png) If you've been following the blog over the last year, you've probably noticed that I've spent quite a bit of time over the last year learning and using Python. For several reasons, it's become my new favor…
Selectively Muting your BFMs to Speed up Simulation
[](/legacy-img/splash-7.png) Have you ever had the misfortune to be on the CC list for a "lively" email discussion where you're a stakeholder but only case about the conclusion? You can't simply ignore the traffic, because you do care about the conclusio…
2019 - The "Nights and Weekends Projects" Year in Review
[](/legacy-img/splash-16.png) It's almost the end of 2019, and I've been thinking back over the year as well as thinking ahead to 2020. In past years, I've often evaluated my "nights and weekends" projects using the same metrics I'm evaluated on at work:…
Writing a Task-Based Cocotb BFM
[](/legacy-img/splash-6.png) Background The purpose of a Bus Functional Model (BFM) is to enable interacting with a design via a given protocol at a higher level of abstraction than the signal-level protocol, while knowing the bare minimum about the…
Adding Task-Based Bus Functional Models to Cocotb
[](/legacy-img/splash-12.png) Getting a project started -- even to a certain level of completeness -- is often pretty simple. A couple weekends of hacking often results in pretty good progress and results. Finishing things up, in contrast, is often…
Embedded Languages: The Space Between Language and API
[](/legacy-img/splash-3.png) We're all familiar with general-purpose programming language for capturing general algorithms, but there are also a sizeable group of domain-specific languages that exist to efficiently capture reasoning in a specific domain -- …
Py-HPI: Applying Python for Verification
[](/legacy-img/splash-5.png) Intro In my [last post](/blog/py-hpi-a-procedural-hdl-python-integration/), I talked about a prototype procedural interface between Python and HDL that enables cross-calling between Python and SystemVerilog. My primar…
Py-HPI: A Procedural HDL/Python Integration
[](/legacy-img/splash-15.png) As I mentioned in my [last post](/blog/functional-verification-and-the-ecosystem-argument/), I've been looking at using Python for more tasks, including functional verification. My go-to languages for functional verifi…
Functional Verification and the Ecosystem Argument
I've been involved in the functional verification space for quite some time -- both personally and professionally. On the personal side, I've recently been experimenting with using Python as a functional verification language. The simplest reason? The ecosyste…
Generate Custom Content Quickly with a Template Engine
[](/legacy-img/vte-splash.png) I was at [DVCon](https://dvcon.org/) earlier this week, and attended the UVM Update Tutorial delivered by Cliff Cummings. Cliff described his typical process of creating UVM elements, which is to have a set of 'golden' temp…