Posts — page 2
Better Coverage Analysis with AI
One near-term outcome of AI's [impact on open source EDA](https://bitsbytesgates.com/eda/2026/02/07/OpenSourceEDAinAIEra.html) is that I've been revisiting and enhancing some of my older projects. [PyUCIS](https://fvutils.github.io/pyucis/), a set of tools fo…
Open Source EDA in the AI Era
AI is changing the world in many ways. This is particularly visible in the commercial software-development space, where AI is often credited with [developing significant portions of new code](https://techcrunch.com/2025/04/29/microsoft-ceo-says-up-to-30-of-t…
Getting Started with Executable Specs
Hardware engineers spend their lives working with specifications, both natual language ("paper") and executable. We've been looking at characterizing the interfaces and internal implementation of executable specifications -- models. But, enough theory. Let's …
Relating Hardware Model Abstractions
The most difficult transition in hardware modeling is the transition from natural-language to executable specification. It is during this transition that the ambiguities inherent in natural-language descriptions are resolved. Maximizing value from a multi-abst…
Shifting Left with Hardware Model Abstractions
"Shift-Left" is a strategy to reorganize processes to enable more parallelism by adjusting dependencies. Hardware model abstractions provide a key tool to shifting tasks left in the silicon design process.
The Best of a Language and a Class Library
In hardware design and verification, we're used to working with domain-specific languages (DSLs), such as SystemVerilog, VHDL, and PSS, as well as class libraries, such as UVM, SystemC, and CHISEL. We use these DSLs and class libraries to capture key semantic…
Embracing UVM for FOSSi Design Verification
Open source communities emphasize reuse and collaboration centered around open and standard data formats. While open source communities do exist in cases where closed-source tools provide the sole implementation of a standard, these communities have significa…
Introducing SV/UVM to Python Development Tools
Over the past few posts, we've examined the details of dynamically interacting with a SystemVerilog/UVM environment from Python. We can access the component hierarchy of a UVM testbench, read and write the value of sequence-item fields, and run sequences from…
Working with Analysis Ports
For the most part, UVM and SystemVerilog make interactions with a dynamically-typed language surprisingly easy. There are a few exceptions where the developer of the SystemVerilog UVM code must step in to enable access to certain testbench elements. Analysis …
Accessing User-Defined SV Data from Python
We've seen how the [PyHDL-IF](http://github.com/fvutils/pyhdl-if) library makes it simple to implement UVM sequences and components in Python, and how Python can call back into SystemVerilog. But, a significant part of a testbench deals with user-defined data…