Posts — page 3
Re-Evaluating EDA DSLs: Becoming the Compiler
A key benefit of full languages is having full control over processing the language: being the compiler. Having full control over language processing is exactly what enables us target simulation and FPGA bitstream with the same SystemVerilog source simply by …
Re-Evaluating EDA DSLs in the AI Era
I've been looking for a new hardware-centric design language for the last couple of years. Or, more precisely, I've been looking for a hardware-centric design language that would allow me to realize my ideal silicon design flow. - Must support using the same…
PSS: Getting Outside the Box
In the [last post](https://bitsbytesgates.com/pss/2025/02/04/TranspilationandPSS.html), we showed a SystemVerilog implementation of a PSS model that printed "Hello World!". Interesting, perhaps, but quite a ways from being useful. In order to be useful, our …
Transpilation and PSS
You're probably familiar with compilers. They take a high-level input description -- typically a programming language -- and distill it down to an efficient low-level implementation. Typically the implementation is machine code or bytecode. In other words, …
What's Next for PSS?
As the year winds down, it's a good time to think about the coming year and the areas where I'd like to have an impact. One area of particular interest this year is the Portable Test and Stimulus (PSS) standard. The Accellera PSS working group released the 3.…
Easy Access to Python Libraries with a SystemVerilog Convenience API
In the last post ([DPI Isn't Enough: Making Python Part of Your SV Testbench](https://bitsbytesgates.com/python/2024/11/04/DPIIsntEnoughMakingPythonPartOfYourSVTB.html)), we looked at how to use the [PyHDL-IF](https://fvutils.github.io/pyhdl-if) library to …
DPI Isn't Enough: Making Python Part of Your SV Testbench
I've been using Python for verification since early 2019 for personal projects, and have found both the language and the rich ecosystem of general and special-purpose libraries to be incredibly helpful in quickly and efficiently bringing up a testbench enviro…
Of Register Models and Standards
Memory-mapped registers play an integral part in configuring and driving the operation of the vast majority of digital designs today. As a consequence, it's not surprising that each language and methodology involved in the design, verification, and documenta…
Relating Actions with Dataflow Part2 -- Parallelism
A few posts back ([Relating Actions with Dataflow](/blog/relating-actions-with-dataflow/)), we talked about using buffer objects to form a relationship between actions that execute sequentially. Because the actions execute sequentially, this relationship lo…
Interacting with Devices via PSS Registers
We've been looking at properly modeling the types of behaviors that we want to exercise on our DMA IP for the last few posts. Of course, until we can actually start programming the DMA registers, all of our modeling won't actually do anything. PSS provides t…