Posts — page 5
Automating Bare-Metal Tests with PSS
As a technologist, it's tempting to focus on what is new (at least, new to me) -- especially when choosing what to write about. I'm periodically reminded that there is immense value in returning to topics. Returning to a topic might raise awareness with a dif…
New Year, New Space
We've more than gotten started on the new year. In fact, DVCon -- reliably and predictably held during the last few days of February and initial few of March is right around the corner. And, here I am just getting the first post of the year out. Getting a la…
Simplifying Custom Template-Generated Content
[](/legacy-img/splash-18.png) As a verification engineer, it's quite common to work with data and code that follow a regular pattern. Having an efficient way to create this repetitive code is a significant productivity boost. While there certainly are p…
PyUCIS: Manipulating Coverage Data
[](/legacy-img/splash-17.png) In a prior post, we looked at how to inspect coverage as a text report and export coverage data using the PyVSC API, and view coverage graphically using the PyUCIS-Viewer. Recent enhancements have enabled the PyUCIS library …
Tools and Techniques to Improve YAML-File Usability
[](/legacy-img/splash-19.png) This blog post is a bit of a departure from many that I’ve created for this blog. Most of my blog posts are about things I’ve created. This post is about a collection of tools that I use in developing the things I create. …
PyVSC: Working with Coverage Data
[](/legacy-img/pyvsccoverage-2.png) I’ve been investing some time in documentation updates this weekend, after a couple of [PyVSC](https://github.com/fvutils/pyvsc) users pointed out some under-described aspects of the PyVSC coverage flow. Given that th…
TbLink-RPC: Simplifying the Multi-Language Testbench
[](/legacy-img/MultiLanguageTestbenchsplash.png) SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s oft…
Documenting SystemVerilog with Sphinx
[](/legacy-img/documenting-systemverilog-with-sphinx-3.png) I've been digging into a project over the last few months whose value proposition is to simplify the process of connecting simulation-like environments and things like reference models, testbenc…
SoC Integration Testing: Hw/Sw Coordination (Part 2)
[](/legacy-img/splash-10.png) Controlling the outside world -- specifically interface BFMs -- from embedded software is critical to SoC integration tests that exercise interface IP. [In the last post](/blog/so-c-integration-testing-hw-sw-test-coordina…
SoC Integration Testing: Hw/Sw Test Coordination (Part 1)
[](/legacy-img/splash-9.png) IP- and subsystem-level testbenches are quite monolithic. There is a single entity (the testbench) that applies stimulus to the design, collects metrics, and checks results. In contrast, an SoC-level testbench is compose…