Posts — page 5
TbLink-RPC: Simplifying the Multi-Language Testbench
[](/legacy-img/MultiLanguageTestbenchsplash.png) SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s oft…
Documenting SystemVerilog with Sphinx
[](/legacy-img/documenting-systemverilog-with-sphinx-3.png) I've been digging into a project over the last few months whose value proposition is to simplify the process of connecting simulation-like environments and things like reference models, testbenc…
SoC Integration Testing: Hw/Sw Coordination (Part 2)
[](/legacy-img/splash-10.png) Controlling the outside world -- specifically interface BFMs -- from embedded software is critical to SoC integration tests that exercise interface IP. [In the last post](/blog/so-c-integration-testing-hw-sw-test-coordina…
SoC Integration Testing: Hw/Sw Test Coordination (Part 1)
[](/legacy-img/splash-9.png) IP- and subsystem-level testbenches are quite monolithic. There is a single entity (the testbench) that applies stimulus to the design, collects metrics, and checks results. In contrast, an SoC-level testbench is compose…
SoC Integration Testing: IP-Integrated Debug and Analysis
[](/legacy-img/splash-8.png) One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I st…
SoC Integration Testing: Higher-Level Software Debug Visibility
[](/legacy-img/splash-14.png) Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping…
SoC Integration Testing: Intro and Challenges
[](/legacy-img/splash.png) As I mentioned in my [end-of-year post](/blog/2020-nights-and-weekends-projects-in-review/), one of my 2020 projects was to develop a design for the [Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run](https://efable…
2020: Nights and Weekends Projects in Review
[](/legacy-img/splash-2.png) 2020 in Review Last year was my first year-end blog post looking back at the prior year's projects, and I thought I'd continue the (now) tradition this year. 2020 has definitely been a different year for me, and not just bec…
Arrays, Dynamic Arrays, Queues: One List to Rule them All
[](/legacy-img/splash-13.png) Randomizable lists are, of course, very important in modeling more-complex stimulus, and I've been working to support these within PyVSC recently. Thus far, PyVSC has attempted to stay as close as possible to both the feature…
Python Verification Stimulus and Coverage: Constraints
[](/legacy-img/splashconstraints.png) Over the past few blog posts, we've looked at: - [The fundamentals of modeling stimulus and functional coverage in Python](/blog/modeling-random-stimulus-and-functional-coverage-in-python/) - [Modeling verificati…