SoC Verification
14 posts
Interacting with Devices via PSS Registers
We've been looking at properly modeling the types of behaviors that we want to exercise on our DMA IP for the last few posts. Of course, until we can actually start programming the DMA registers, all of our modeling won't actually do anything. PSS provides t…
Modeling DMA Test Scenarios with PSS
If you've been following the blog for any length of time, you've likely noticed that I like to work with examples and applications when it comes to learning and understanding technology. I certainly like the tendency of applications to take knowledge out of t…
Declarative Programming and Multi-Core Tests
As humans, we often pride ourselves on our ability to multi-task. Not only can we participate in a meeting, we can we simultaneously prepare the slides for the next meeting. Sadly, science has some bad news about our perception to multitask vs our actual ab…
PSS Fundamentals: Actions, Components, and Test Generation
Complex engineering endeavors require complex calculations. It's open to debate as to when the first engineering project that required complex calculations occurred. What we do know is that those calculations would have been done by hand. And this state la…
Automating Bare-Metal Tests with PSS
As a technologist, it's tempting to focus on what is new (at least, new to me) -- especially when choosing what to write about. I'm periodically reminded that there is immense value in returning to topics. Returning to a topic might raise awareness with a dif…
SoC Integration Testing: Hw/Sw Coordination (Part 2)
[](/legacy-img/splash-10.png) Controlling the outside world -- specifically interface BFMs -- from embedded software is critical to SoC integration tests that exercise interface IP. [In the last post](/blog/so-c-integration-testing-hw-sw-test-coordina…
SoC Integration Testing: Hw/Sw Test Coordination (Part 1)
[](/legacy-img/splash-9.png) IP- and subsystem-level testbenches are quite monolithic. There is a single entity (the testbench) that applies stimulus to the design, collects metrics, and checks results. In contrast, an SoC-level testbench is compose…
SoC Integration Testing: IP-Integrated Debug and Analysis
[](/legacy-img/splash-8.png) One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I st…
SoC Integration Testing: Higher-Level Software Debug Visibility
[](/legacy-img/splash-14.png) Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping…
SoC Integration Testing: Intro and Challenges
[](/legacy-img/splash.png) As I mentioned in my [end-of-year post](/blog/2020-nights-and-weekends-projects-in-review/), one of my 2020 projects was to develop a design for the [Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run](https://efable…
2020: Nights and Weekends Projects in Review
[](/legacy-img/splash-2.png) 2020 in Review Last year was my first year-end blog post looking back at the prior year's projects, and I thought I'd continue the (now) tradition this year. 2020 has definitely been a different year for me, and not just bec…
System Level Verification: What, Another Framework?
Frameworks have been enormously helpful in making testing and verification productive and reusable. In the RTL verification space, AVM, VMM, OVM, and UVM have all contributed to standardizing a pattern for RTL verification that encompasses encapsulation and re…
System-level verification: Islands vs Continents
As the saying goes, "There is nothing permanent except change". However, even with constant change, similarities with what came before abound and true and complete discontinuities are relatively rare. This is certainly true in the functional verification space…
Verification Frameworks and System-Level Verification
It seems the last decade or so has been the decade of the verification language and the verification framework. From SystemC, Vera, and 'e' to SystemVerilog, and VMM and AVM to OVM and UVM, a lot of focus has been placed on making design verification engineers…