UVM
19 posts
Embracing UVM for FOSSi Design Verification
Open source communities emphasize reuse and collaboration centered around open and standard data formats. While open source communities do exist in cases where closed-source tools provide the sole implementation of a standard, these communities have significa…
Introducing SV/UVM to Python Development Tools
Over the past few posts, we've examined the details of dynamically interacting with a SystemVerilog/UVM environment from Python. We can access the component hierarchy of a UVM testbench, read and write the value of sequence-item fields, and run sequences from…
Working with Analysis Ports
For the most part, UVM and SystemVerilog make interactions with a dynamically-typed language surprisingly easy. There are a few exceptions where the developer of the SystemVerilog UVM code must step in to enable access to certain testbench elements. Analysis …
Accessing User-Defined SV Data from Python
We've seen how the [PyHDL-IF](http://github.com/fvutils/pyhdl-if) library makes it simple to implement UVM sequences and components in Python, and how Python can call back into SystemVerilog. But, a significant part of a testbench deals with user-defined data…
The Mechanics of UVM/Python Cross-Calling
It's not necessary to understand very much about how PyHDL-IF implements the bridge between Python and UVM, but useful to understand a bit. Doing so helps to understand what this library is and is not intended to do, and how you can best use it in your verifi…
Unlocking the Combined Strength of UVM and Python
UVM and Python are often positioned as rivals when it comes to their role in functional verification, with teams picking one or the other as the basis for a verification environments. Each have strengths, though, and using them together produces much strong…
Re-Evaluating EDA DSLs in the AI Era
I've been looking for a new hardware-centric design language for the last couple of years. Or, more precisely, I've been looking for a hardware-centric design language that would allow me to realize my ideal silicon design flow. - Must support using the same…
Easy Access to Python Libraries with a SystemVerilog Convenience API
In the last post ([DPI Isn't Enough: Making Python Part of Your SV Testbench](https://bitsbytesgates.com/python/2024/11/04/DPIIsntEnoughMakingPythonPartOfYourSVTB.html)), we looked at how to use the [PyHDL-IF](https://fvutils.github.io/pyhdl-if) library to …
DPI Isn't Enough: Making Python Part of Your SV Testbench
I've been using Python for verification since early 2019 for personal projects, and have found both the language and the rich ecosystem of general and special-purpose libraries to be incredibly helpful in quickly and efficiently bringing up a testbench enviro…
Of Register Models and Standards
Memory-mapped registers play an integral part in configuring and driving the operation of the vast majority of digital designs today. As a consequence, it's not surprising that each language and methodology involved in the design, verification, and documenta…
Interacting with Devices via PSS Registers
We've been looking at properly modeling the types of behaviors that we want to exercise on our DMA IP for the last few posts. Of course, until we can actually start programming the DMA registers, all of our modeling won't actually do anything. PSS provides t…
Simplifying Custom Template-Generated Content
[](/legacy-img/splash-18.png) As a verification engineer, it's quite common to work with data and code that follow a regular pattern. Having an efficient way to create this repetitive code is a significant productivity boost. While there certainly are p…
TbLink-RPC: Simplifying the Multi-Language Testbench
[](/legacy-img/MultiLanguageTestbenchsplash.png) SystemVerilog/UVM is, by far, the most widely-used language and methodology for block and subsystem-level verification environments today. The simplicity of that statement overlooks the fact that it’s oft…
SoC Integration Testing: IP-Integrated Debug and Analysis
[](/legacy-img/splash-8.png) One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I st…
Embedded Languages: The Space Between Language and API
[](/legacy-img/splash-3.png) We're all familiar with general-purpose programming language for capturing general algorithms, but there are also a sizeable group of domain-specific languages that exist to efficiently capture reasoning in a specific domain -- …
Generate Custom Content Quickly with a Template Engine
[](/legacy-img/vte-splash.png) I was at [DVCon](https://dvcon.org/) earlier this week, and attended the UVM Update Tutorial delivered by Cliff Cummings. Cliff described his typical process of creating UVM elements, which is to have a set of 'golden' temp…
DVKit: Setting up SystemVerilog Development
[](/legacy-img/Headlinefull-2.png) In my [last post](/blog/dvkit-workspaces-projects-and-legacy-code/) on DVKit, I described how Eclipse uses projects to group source files, and uses workspaces to organize the projects and settings for a given developmen…
Chisel Sharpening: If it's not tested, it's broken
"If it's not tested, it's broken." -- [Bruce Eckel](http://www.inspiringquotes.us/author/9711-bruce-eckel) I'm a big believer in the quote above, and cite it somewhat frequently -- perhaps to the tedium of my colleagues. In my last post, I showed a Chise…
System Level Verification: What, Another Framework?
Frameworks have been enormously helpful in making testing and verification productive and reusable. In the RTL verification space, AVM, VMM, OVM, and UVM have all contributed to standardizing a pattern for RTL verification that encompasses encapsulation and re…