Posts — page 7
Py-HPI: Applying Python for Verification
[](/legacy-img/splash-5.png) Intro In my [last post](/blog/py-hpi-a-procedural-hdl-python-integration/), I talked about a prototype procedural interface between Python and HDL that enables cross-calling between Python and SystemVerilog. My primar…
Py-HPI: A Procedural HDL/Python Integration
[](/legacy-img/splash-15.png) As I mentioned in my [last post](/blog/functional-verification-and-the-ecosystem-argument/), I've been looking at using Python for more tasks, including functional verification. My go-to languages for functional verifi…
Functional Verification and the Ecosystem Argument
I've been involved in the functional verification space for quite some time -- both personally and professionally. On the personal side, I've recently been experimenting with using Python as a functional verification language. The simplest reason? The ecosyste…
Generate Custom Content Quickly with a Template Engine
[](/legacy-img/vte-splash.png) I was at [DVCon](https://dvcon.org/) earlier this week, and attended the UVM Update Tutorial delivered by Cliff Cummings. Cliff described his typical process of creating UVM elements, which is to have a set of 'golden' temp…
EDAPack: Simplifying Development-Tool Management
[](/legacy-img/edapack-splash.png) One of my first "real" engineering courses during my college days centered around scripting and working with Unix, and the professor really emphasized that any repetitive task was a candidate for automation. It's a poi…
FWRISC: Creating a Unit-test Safety Net
[](/legacy-img/unittestsplash.png) When developing software, I've become very comfortable with test-driven development -- a methodology that calls for tests to be developed along with, or even before, functionality. It's quite common for me to develop a …
FWRISC: Sizing up the RISC-V Architecture
[](/legacy-img/post2intro.png) After deciding on October 22nd to create a RISC-V implementation to enter in the [2018 RISC-V soft-core contest](https://riscv.org/2018contest/) (with entries due November 26th), I needed to gather more information of th…
FWRISC: Designing an FPGA-friendly Core in 30 Days
[](/legacy-img/fwriscintrosplash2.png) Designing a processor is often considered to be a large and complex undertaking, so how did I decide to design and implement in a month? For a few reasons, really. For one, my background is in hardware design, despit…
Why Not an IDE?
As anyone (technical) who knows me can attest, I'm a big fan of Integrated Development Environments (IDEs). I've personally focused particularly on the [Eclipse](http://eclipse.org/) IDE, but I'm more generally a fan of the concept -- the notion that the task …
DVKit: Setting up SystemVerilog Development
[](/legacy-img/Headlinefull-2.png) In my [last post](/blog/dvkit-workspaces-projects-and-legacy-code/) on DVKit, I described how Eclipse uses projects to group source files, and uses workspaces to organize the projects and settings for a given developmen…