UVM and Python
5 parts, in reading order.
Unlocking the Combined Strength of UVM and Python
UVM and Python are often positioned as rivals when it comes to their role in functional verification, with teams picking one or the other as the basis for a verification environments. Each have strengths, though, and using them together produces much strong…
The Mechanics of UVM/Python Cross-Calling
It's not necessary to understand very much about how PyHDL-IF implements the bridge between Python and UVM, but useful to understand a bit. Doing so helps to understand what this library is and is not intended to do, and how you can best use it in your verifi…
Accessing User-Defined SV Data from Python
We've seen how the [PyHDL-IF](http://github.com/fvutils/pyhdl-if) library makes it simple to implement UVM sequences and components in Python, and how Python can call back into SystemVerilog. But, a significant part of a testbench deals with user-defined data…
Working with Analysis Ports
For the most part, UVM and SystemVerilog make interactions with a dynamically-typed language surprisingly easy. There are a few exceptions where the developer of the SystemVerilog UVM code must step in to enable access to certain testbench elements. Analysis …
Introducing SV/UVM to Python Development Tools
Over the past few posts, we've examined the details of dynamically interacting with a SystemVerilog/UVM environment from Python. We can access the component hierarchy of a UVM testbench, read and write the value of sequence-item fields, and run sequences from…