Posts — page 9
Designing Standard-protocol Interfaces with Chisel Bundles
[](/legacy-img/plugboard2.jpg) Standard interfaces are all around us, and enhance interoperability between devices created by different organizations. While some standard interfaces are quite niche in nature, others, like the unbiquitous phono jack, have …
Chisel Sharpening: In the end, it's all about results
At the end of the day, it's all about results, of course. A productivity improvement is great, as long as the implementation results at least stay constant. Any decrease in implementation results definitely detract from any productivity improvements. So, …
Chisel Sharpening: If it's not tested, it's broken
"If it's not tested, it's broken." -- [Bruce Eckel](http://www.inspiringquotes.us/author/9711-bruce-eckel) I'm a big believer in the quote above, and cite it somewhat frequently -- perhaps to the tedium of my colleagues. In my last post, I showed a Chise…
Chisel Sharpening: Initial impressions
Recently, RiscV () has been all the rage. The free (as in speech and beer) instruction-set architecture has experienced an explosion of interest in the last couple of years, after being more-or-less an academic curiosity since 2010 or so. This post isn't …
System Level Verification: What, Another Framework?
Frameworks have been enormously helpful in making testing and verification productive and reusable. In the RTL verification space, AVM, VMM, OVM, and UVM have all contributed to standardizing a pattern for RTL verification that encompasses encapsulation and re…
System-level verification: Islands vs Continents
As the saying goes, "There is nothing permanent except change". However, even with constant change, similarities with what came before abound and true and complete discontinuities are relatively rare. This is certainly true in the functional verification space…
Verification Frameworks and System-Level Verification
It seems the last decade or so has been the decade of the verification language and the verification framework. From SystemC, Vera, and 'e' to SystemVerilog, and VMM and AVM to OVM and UVM, a lot of focus has been placed on making design verification engineers…
SVEditor: What's that reference? (Part 1)
One key feature of integrated development environments -- especially those for object oriented languages -- is the ability to find the references to a data type, a method, or a data field. A few months back, I implemented initial reference-finding functionalit…