SoC Integration Testing
5 parts, in reading order.
SoC Integration Testing: Intro and Challenges
[](/legacy-img/splash.png) As I mentioned in my [end-of-year post](/blog/2020-nights-and-weekends-projects-in-review/), one of my 2020 projects was to develop a design for the [Google/eFabless/SkyWater Multi-Project Wafer (MPW) fab run](https://efable…
SoC Integration Testing: Higher-Level Software Debug Visibility
[](/legacy-img/splash-14.png) Debug is a key task in any development task. Whether debugging application-level software or a hardware design, a key to productive debug is getting a higher-level view of what is happening in the design. Blindly stepping…
SoC Integration Testing: IP-Integrated Debug and Analysis
[](/legacy-img/splash-8.png) One of the things I've always liked about side projects is the freedom to stop and explore a topic of interest as it comes up. One such topic that came up for me recently is IP-integrated debug and analysis instrumentation. I st…
SoC Integration Testing: Hw/Sw Test Coordination (Part 1)
[](/legacy-img/splash-9.png) IP- and subsystem-level testbenches are quite monolithic. There is a single entity (the testbench) that applies stimulus to the design, collects metrics, and checks results. In contrast, an SoC-level testbench is compose…
SoC Integration Testing: Hw/Sw Coordination (Part 2)
[](/legacy-img/splash-10.png) Controlling the outside world -- specifically interface BFMs -- from embedded software is critical to SoC integration tests that exercise interface IP. [In the last post](/blog/so-c-integration-testing-hw-sw-test-coordina…